This invention relates to the field of circuit design. In particular, this invention is drawn to common mode feedback circuits and methods of calibrating such circuits to minimize the common mode current to differential mode voltage conversion factor.
Common mode feedback circuits are routinely incorporated into the design of differential circuits when a differential pair of signal nodes must present a low impedance to common mode excitation without significantly affecting the differential mode excitation of the circuitry. Asymmetries within the common mode feedback circuit, however, may impair the common mode feedback circuit ability to reject common mode signals. This results in degradation of the performance of the differential circuitry.
In order to improve the performance of the differential circuitry, the common mode feedback circuit may be designed as an adjustable component of the differential circuitry. The common mode feedback circuit is adjusted or calibrated to maximize rejection of the common mode component of any signal presented to a differential node pair of the differential circuitry.
Typically, adjusting or tuning of the common mode feedback circuit requires the application of a matched pair of signal sources (e.g., current sources) to the differential node pair. The primary disadvantage of this approach is the requirement for highly matched external current sources. The calibration of the common mode feedback circuitry is limited by the precision of matching between the external current sources.
Another approach calibrates the common mode feedback circuitry based on the external current sources and memorizes the result. The differential nodes are then switched so that the current sources are now presented to the complementary nodes as compared with the first calibration run. A second calibration now calibrates the common mode feedback circuitry based on the swapped current sources. The calibration mechanism then attempts to find an optimum adjustment based on the two stored calibration results. Although this approach is less reliant on precise matching of the external current sources, the calibration procedure and calibration engine are necessarily more complex.
A common mode feedback circuit includes first and second nodes defining a differential node pair. A collective plurality of transconductors includes a first plurality of transconductors associated with the first node and a second plurality of transconductors associated with the second node. At least one transconductor of the collective plurality has an adjustable transconductance. In one embodiment, each node has at least one transconductor with an adjustable transconductance. The nominal transconductance of each of the transconductors within a selected plurality is substantially the same.
The common mode feedback circuit may further include a calibration engine. While in a calibration mode, the calibration engine adjusts at least one adjustable transconductor until a sensed differential voltage across the differential node pair is substantially zero without the use of external current sources. When switched to a normal mode, the calibration fixes the adjustable transconductance values to prevent further adjustments.
In various embodiments, the common mode feedback block including the calibration engine resides on an integrated circuit semiconductor die. In one embodiment, the common mode feedback block is fabricated as a complementary metal oxide semiconductor (CMOS) integrated circuit.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.